/* Copyright (C) 2011. ChengDu Unicon system, All Rights Reserved */

/*""FILE COMMENT""******************************* Technical reference data ****
* File Name	: 
* Version 	: 1.00
* Device 	: SH72543
* Tool Chain 	: 
* H/W Platform	: 
* Description 	: 
******************************************************************************/

/******************************************************************************
* History 	: 
*		: 
*FILE COMMENT END*********************************************************/

#ifndef SPARK_CONTROL_H
#define SPARK_CONTROL_H

#include "cpu.h"

/* Define Spark Control Pin Init */
/* Spark 1 */
#define SPARK_1COM_INIT PORTD.CR1.BIT.MD0 = 1;\
                        PORTD.IR.BIT.IR0  = 0  /* Spark 1 Timer Pluse, PORTD0 is TIOC00 output,The set value is not inverted when output */

#define SPARK_1A_INIT PORTC.CR1.BIT.MD0  = 0;\
                      PORTC.DR.BIT.DR0   = 0;\
                      PORTC.IOR.BIT.IOR0 = 1  /* Spark 1A Enable Control */

#define SPARK_1B_INIT PORTC.CR2.BIT.MD4  = 0;\
                      PORTC.DR.BIT.DR4   = 0;\
                      PORTC.IOR.BIT.IOR4 = 1  /* Spark 1B Enable Control */
/* Spark 2 */
#define SPARK_2COM_INIT PORTD.CR1.BIT.MD1 = 1;\
                        PORTD.IR.BIT.IR1  = 0  /* Spark 2 Timer Pluse */

#define SPARK_2A_INIT PORTC.CR1.BIT.MD1  = 0;\
                      PORTC.DR.BIT.DR1   = 0;\
                      PORTC.IOR.BIT.IOR1 = 1  /* Spark 2A Enable Control */

#define SPARK_2B_INIT PORTC.CR2.BIT.MD5  = 0;\
                      PORTC.DR.BIT.DR5   = 0;\
                      PORTC.IOR.BIT.IOR5 = 1  /* Spark 2B Enable Control */

/* Spark 3 */
#define SPARK_3COM_INIT PORTD.CR1.BIT.MD2 = 1;\
                        PORTD.IR.BIT.IR2  = 0  /* Spark 3 Timer Pluse */

#define SPARK_3A_INIT PORTC.CR1.BIT.MD2  = 0;\
                      PORTC.DR.BIT.DR2   = 0;\
                      PORTC.IOR.BIT.IOR2 = 1  /* Spark 3A Enable Control */

#define SPARK_3B_INIT PORTC.CR2.BIT.MD6  = 0;\
                      PORTC.DR.BIT.DR6   = 0;\
                      PORTC.IOR.BIT.IOR6 = 1  /* Spark 3B Enable Control */

#define SparkEnOut(sparkChannel) PORTC.DR.WORD &= (CPU_INT16U)((sparkChannel & 0x0007) | ((sparkChannel << 1) & 0x0070)) | 0xFF88                       
                        
#define SPARK_1A_EN   PORTC.DR.BIT.DR0=1
#define SPARK_1A_DIS  PORTC.DR.BIT.DR0=0

#define SPARK_1B_EN   PORTC.DR.BIT.DR4=1
#define SPARK_1B_DIS  PORTC.DR.BIT.DR4=0

#define SPARK_2A_EN   PORTC.DR.BIT.DR1=1
#define SPARK_2A_DIS  PORTC.DR.BIT.DR1=0

#define SPARK_2B_EN   PORTC.DR.BIT.DR5=1
#define SPARK_2B_DIS  PORTC.DR.BIT.DR5=0

#define SPARK_3A_EN   PORTC.DR.BIT.DR2=1
#define SPARK_3A_DIS  PORTC.DR.BIT.DR2=0

#define SPARK_3B_EN   PORTC.DR.BIT.DR6=1
#define SPARK_3B_DIS  PORTC.DR.BIT.DR6=0

/* Define Spark Timer Interrupt Priority Register */
#define sparkTimerIntPrio   INTC.IPR07.BIT.IPL_IMIC00_03
/* Timer Define */
#define TIMER_BASE_INIT     ATUC.SUBBLOCK[0].TCRC.BIT.CKSELC = 0
#define TIMER_CLOCK_SET     ATUC.SUBBLOCK[0].TCRC.BIT.CKSELC = 0 //Clock Bus 0
#define sparkTimer1CycleReg ATUC.SUBBLOCK[0].GRC[0]
#define sparkTimer2CycleReg ATUC.SUBBLOCK[0].GRC[1]
#define sparkTimer3CycleReg ATUC.SUBBLOCK[0].GRC[2]
#define sparkTimerCounter   ATUC.SUBBLOCK[0].TCNTC
#define SPARK_TIMER_START   ATUC.TSTRC.BIT.STRC0 = 1
#define SPARK_TIMER_STOP    ATUC.TSTRC.BIT.STRC0 = 0



/* Be used to Timer I/O Control Registers Value Set */
#define CMFD  0 //Compare match function disabled
#define CMO0  1 //Logical zero is output on compare match
#define CMO1  2 //Logical one is output on compare match
#define CMO10 3 //Output levels are toggled every compare match
/* Define Timer Control Registers */
#define sparkTimer1ForcedMatch ATUC.SUBBLOCK[0].TCRC.BIT.FCMC0
#define sparkTimer2ForcedMatch ATUC.SUBBLOCK[0].TCRC.BIT.FCMC1
#define sparkTimer3ForcedMatch ATUC.SUBBLOCK[0].TCRC.BIT.FCMC2
/* Define Timer Status Registers */
#define sparkTimer1MatchFlag   ATUC.SUBBLOCK[0].TSRC.BIT.IMFC0
#define sparkTimer2MatchFlag   ATUC.SUBBLOCK[0].TSRC.BIT.IMFC1
#define sparkTimer3MatchFlag   ATUC.SUBBLOCK[0].TSRC.BIT.IMFC2
#define sparkTimerOverflowFlag ATUC.SUBBLOCK[0].TSRC.BIT.OVFC
/* Define Timer Interrupt Enable Registers */
#define sparkTimer1MatchInt ATUC.SUBBLOCK[0].TIERC.BIT.IMEC0
#define sparkTimer2MatchInt ATUC.SUBBLOCK[0].TIERC.BIT.IMEC1
#define sparkTimer3MatchInt ATUC.SUBBLOCK[0].TIERC.BIT.IMEC2
/* Define Timer I/O Control Registers */
#define sparkTimer1Out      ATUC.SUBBLOCK[0].TIORC.BIT.IOC0
#define sparkTimer2Out      ATUC.SUBBLOCK[0].TIORC.BIT.IOC1
#define sparkTimer3Out      ATUC.SUBBLOCK[0].TIORC.BIT.IOC2
#define SPARK_TIMER_CLOSE   0 //Compare match function disabled
#define SPARK_COIL_OFF      1 //Logical zero is output on compare match
#define SPARK_COIL_ON       2 //Logical one is output on compare match

#define SPARK1A 1
#define SPARK1B 2
#define SPARK2A 4
#define SPARK2B 8
#define SPARK3A 16
#define SPARK3B 32

#define SPARK_TIMER_FORCED_MATCH 1
#define SPARK_TIMER_INT_OPEN     1
#define SPARK_TIMER_INT_CLOSE    0

typedef struct
{
  union
  {
    CPU_INT08U byte;
    struct
    {
      CPU_INT08U        :2;
      CPU_INT08U spark3B :1;
      CPU_INT08U spark3A :1;
      CPU_INT08U spark2B :1;
      CPU_INT08U spark2A :1;
      CPU_INT08U spark1B :1;
      CPU_INT08U spark1A :1;      
    }bit;    
  }enable;
  struct
  {
    CPU_INT32U ready :24;
    CPU_INT32U       :8;
    CPU_INT32U charge:24;
    CPU_INT32U       :8;
  }timer;
}st_sparkReg;

extern void SparkTimer1ISRHandler( void );

#endif